In semiconductor memory devices, data is read from or written to memory cells in the device according to decoded address information and various other control signals. Such memory devices are used for storage of data and/or program code in personal computer systems, embedded processor-based systems, video image processing circuits, and the like. Ferroelectric memories are commonly organized in single-transistor, single-capacitor (1T1C) or two-transistor, two-capacitor (2T2C) configurations, in which each memory cell includes one or more access transistors, as is generally known. In a folded bitline architecture, the individual ferroelectric memory cells typically include a ferroelectric (FE) capacitor adapted to store a binary data bit, together with a MOS access transistor, which operates to selectively connect the FE capacitor to one of a pair of complementary bitlines, with the other bitline being connected to a reference voltage for read operations. The individual cells are commonly organized as individual bits of a corresponding data word, where the cells of a given word are accessed concurrently by activation of platelines and wordlines by address decoding control circuitry.
Such ferroelectric memory devices provide non-volatile data storage where the data cell capacitors are constructed using ferroelectric dielectric material which may be polarized in one direction or another in order to store a binary value. The ferroelectric effect allows for the retention of a stable polarization in the absence of an applied electric field due to the alignment of internal dipoles within Perovskite crystals in the dielectric material. This alignment may be selectively achieved by application of an electric field which exceeds the coercive field of the material. Conversely, reversal of the applied field reverses the internal dipoles. The response of the polarization of a ferroelectric capacitor to the applied voltage may be plotted as a hysteresis curve.
Data in a ferroelectric data cell is read by connecting a reference voltage to a first bitline and connecting the cell capacitor between a complementary bitline and a plateline signal. This provides a differential voltage on the bitline pair, which is connected to a differential sense amp circuit. The reference voltage is typically supplied at an intermediate voltage between the voltage associated with a capacitor charged to a binary “0” and that of the capacitor charged to a binary “1”. The polarity of the sensed differential voltage thus represents the data stored in the cell, which is buffered by the sense amp and provided to a pair of local IO lines. The transfer of data between the ferroelectric memory cell, the sense amp circuit, and the local data bitlines is controlled by various access transistors, typically MOS devices, with switching signals being provided by control circuitry including address decoders and timing circuits in the device.
Connection of the ferroelectric cell capacitor between the plateline pulse and the bitline during a read operation causes an electric field to be applied to the cell capacitor. If the field is applied in a direction to switch or reverse the internal dipoles, more charge will be moved than if the dipoles are not reversed. As a result, the sense amplifier can measure the charge applied to the cell bit lines and produce either a logic “1” or “0” differential voltage at the sense amp terminals. Since reading the cell data is a destructive operation, the sensed data is then restored to the cell following each read operation. To write data to the cell, an electric field is applied to the cell capacitor by a sense amp or write buffer to polarize it to the desired state. Ferroelectric memories provide certain performance advantages over other forms of non-volatile data storage devices, such as flash and EEPROM type memories. For example, ferroelectric memories offer short programming (e.g., write access) times and low power consumption.
Ferroelectric memory devices typically include a number of individually addressable memory cells arranged in an array configuration, wherein the array is typically organized as a matrix of rows and columns. Conventionally, data is stored into a memory array as a row, and read out from the memory array as a row, where the row typically consists of 8, 16, 32, or 64 bits of binary data. During a write operation, row decoder control circuitry provides a plateline pulse signal to the first sides of the ferroelectric cells in a data row, the other sides of which are connected to the write data. In a read operation, the decoder provides plate line pulses to the first side of each ferroelectric memory cell in a data row, and sense amplifiers are connected to the other side of the cells to sense a row of stored data bits in parallel fashion. Thus, in a single read operation, an entire row of data bits (e.g., 8, 16, 32, or 64 bits) are obtained from the memory cells in the selected row.
FIG. 1 illustrates a portion of a ferroelectric memory device 2 organized in a folded bitline architecture, having 512 rows (words) and 64 columns (bits) of data storage cells CROW-COLUMN, where each column of cells is accessed via a pair of complementary bitlines BLCOLUMN and BLCOLUMN′. In the first row of the device 2, for example, the cells C1-1 through C1-64 form a 64 bit data word accessible via a wordline WL1 and complementary bitline pairs BL1/BL1′ through BL64/BL64′. The cell data is sensed during data read operations using sense amp circuits 12 (S/A C1 through S/A C64) associated with columns 1 through 64, respectively. In the illustrated configuration, the 1T1C cells CROW-COLUMN individually include a single ferroelectric cell capacitor and an access transistor to connect the cell capacitor between one of the complementary bitlines associated with the cell column and a plateline, where the other bitline is selectively connected to a reference voltage for read operations.
In the device 2, the sense amps 12 associated with even numbered columns are located at the top of the segment, and the sense amps 12 associated with odd numbered columns are located at the bottom of the segment. Shared reference generators 8 and 8′ are provided at the top and bottom of the segment columns, respectively. The even column reference generator 8 provides a reference voltage for even numbered columns and the odd column reference generator 8′ is provided for the odd numbered columns. The reference voltages from the generators 8, 8′ are coupled to one of the bitlines in the columns by one of a pair of switches 8a, 8b, depending upon whether an even or odd numbered wordline is selected. In reading the first data word along the wordline WL1, the cells C1-1 through C1-64 are connected to the sense amps via the bitlines BL1, BL2 . . . , BL63, and BL64 while the complementary reference bitlines BL1′, BL2′ . . . , BL63′, and BL64′ are connected to the reference voltage generators 8, 8′.
During a read operation in a conventional folded bitline ferroelectric memory, a signal level V1 or V0 is thus obtained on the data bitline (e.g., the bitline coupled with the accessed cell), depending upon the state of the data being read (e.g., binary “1” or “0”, respectively). The reference voltage from the shared reference generators 8, 8′ is thus ideally a voltage VREF in between V1 and V0, which is then applied to the complementary bitline before the sense amps 12 are enabled. Thusfar, two types of reference generation schemes have been employed in ferroelectric memory devices. In the first type (e.g., FIG. 1), a single reference generator is common to (e.g., shared by) several columns. In a second approach, a separate (e.g., dedicated) reference generator is provided for each column. A problem with the first approach is that several reference bitlines are sorted together through the common reference generator during read operations. In this situation, a bad column cannot be distinguished or isolated from other (e.g., presumably good) columns, thus making replacement or substitution impossible for a single bad column, where column redundancy is employed.
However, several challenges are presented in implementing the second approach, including reliability, area utilization, and power consumption. In the past, the generated reference voltage in such dedicated reference generator architectures is often a function of bitline capacitance, leading to variation in VREF for different array columns. Accordingly, there remains a need for improved apparatus and methods for providing reference voltages for ferroelectric memory devices, by which the above and other shortcomings of the prior art may be mitigated or overcome.